The present invention relates to a semiconductor device in which a standby interval for reducing power consumption is provided, and in which an external power supply voltage is dropped so as to generate a lower voltage level than the external power supply voltage. This voltage is used as the internal voltage of the semiconductor device.
Recently, integrated circuits (ICs) using MOS transistors having an effective channel length of about 1 .mu.m or less have been developed. In MOS transistors having a reduced effective channel length, when a voltage of 5 V, which is standard for transistor-transistor logic (TTL), is directly applied to the drain of an internal transistor, hot carriers are generated, thereby causing an undesirable gate current. Furthermore, the gate current is partially trapped by a trapping center in the gate insulation film and the gate insulation film is charged, thereby gradually changing the threshold voltage of the MOS transistor.
In order to prevent such a disadvantage, in the case wherein the external power supply voltage is 5 V, a voltage of 5 V or less, for example, 3 V, is obtained from the voltage of 5 V inside the semiconductor device. Then, this voltage of 3 V is applied to the MOS transistor having the reduced effective channel length. In this case, a voltage dropping circuit for dropping the external power supply voltage of 5 V so as to obtain a voltage of 3 V is needed. Such voltage dropping circuits are well-known as described in "Submicron VLSI Memory circuits", ISSCC Digest of Technical Papers, 1983, pp 234-235 by T. Mano et al, or in "An Experimental 1 Mb DRAM with On-Chip Voltage Limiter", ISSCC Digest of Technical Papers, 1984, pp 282-283 by K. Ito et al.
On the other hand, a semiconductor device such as a semiconductor memory having a so-called standby interval is also known. During the standby interval, an internal circuit is substantially stopped, and power consumption is reduced more than in the normal operating mode. During the standby interval, in order to control the overall power consumption of the semiconductor device, the power consumption in the voltage dropping circuit is preferably reduced. Then, in order to reduce power consumption in the voltage dropping circuit, the voltage dropping circuit is also stopped during the standby interval. However, in a semiconductor memory, more particularly, in a dynamic memory, since data holding is performed during the standby interval, the same power supply voltage as in the normal operating mode must be supplied. When the power supply voltage is abnormally low or high, data is destroyed, and normal operation after the standby interval cannot be expected. Therefore, it is not preferred to stop the power supply in the manner as described above, and the operation of the voltage dropping circuit cannot be stopped. In order to minimize the power consumption of the voltage dropping circuit without interrupting its operation, the voltage dropping circuit may be designed to minimize the current flowing thereto. However, when a current value is reduced so as to control the power consumption, the response time of the voltage which is dropped as an output voltage lags, and the constant voltage characteristic is lost.
In this manner, in a conventional voltage dropping circuit, a constant current flows therein during the standby interval. However, this current is useless and a back-up operation using a battery cannot be performed because of this current. Note that a current consumption of 2 mA is necessary to obtain a sufficient constant voltage characteristic in the conventional voltage dropping circuit. However, in order to perform a back-up operation using a battery, the current consumption must be controlled to be below 100 .mu.A.